5. Configure a fastAdc device

Please consider that the following configuration steps should be performed by experts; a wrong setting will result in a device not properly working.

5.1. Configuration step by step

  • Configuration
  • Set Device File to the latest version of /dev/pciedevs?. Now we have pciedevs6 for SA2 and pciedevs7 for SCS;
  • Set Map Directory to /home/xctrl/maps. This folder contains the configuration xml-files of the firmware registers.
  • Change Board Configuration / FPGA Source Clock to TCLKA.
  • Instantiate the fastAdc device. Now Train ID should be updating. If not or the value is some unreasonable number, please contact AE.
  • By default, the channels are closed. To enable a channel, set Enable Peak Computation and Enable Raw Data to True.
  • After you have done the previous steps correctly, Baseline Value and Mean Peak Value should be updating. If you have a scene, then you should see some noise. However, if nothing for the channel is updating and there is only a flat line in the scene (a single number), you are trapped by a bug in the firmware. Some discussions can be found in the redmine ticket #28462. You can fix it contacting AE. Anyway, the latest device release provides in the configuration editor the option to reset the DDR2 memory (in the SIS8300 board, where the raw ADC data are stored) and/or the ADC chip, clearing the above mentioned firmware bug.